[ČE] Digital electronics

BCKIS

[ČE] Digital electronics

Main objectives of the course:

Course information sheet
University: University of Žilina
Faculty: Faculty of Management Science and Informatics
Course ID: 5BF118Course name: Digital electronics (ČE)
Form, extent and method of teaching activities:
Number of classes per week in the form of lectures,
laboratory exercises, seminars or clinical practice
Lectures: 2.0 Seminars: 0.0 Lab.exercises: 2.0
Methods by which the educational activity is deliveredPresent form of education
Applied educational activities and methods suitable for achieving learning outcomes
Number of credits: 5.0
Study workload: hours
Specification of the study workload:
Recommended term of study: 2. year, summer semester
Study degree: 1.
Required subsidiary courses:
Prerequisites:

Co-requisites:
Course requirements:
Continuous assessment / evaluation:
- Semester work (max. 30 points)
- Activity in exercises (e.g. solving specific tasks) - max. 10 points
Final assessment /evaluation:
The condition for successful completion of the course is to gain at least 61 out of 100 points for work in the semester and to pass an exam in the course. The exam is written, the tasks will be focused on the practical solution of examples as well as on the demonstration of theoretical knowledge.
Final evaluation of the course:
100 - 92 points A
91 - 84 points B
83 - 76 points C
75 - 68 points D
67 - 61 points E
60 or less points Fx
To enroll for an exam student must have - points.
Course outcomes:
By studying the course, the student will gain basic knowledge in the field of combinational and sequential logic systems, which allows them to use them in the analysis and synthesis of simple digital systems.
By studying the course, the student will gain basic knowledge about the design of combinational and sequential circuits based on the description of the architecture in VHDL.
Course scheme:
Lectures:

1. Terminology, definition of terms. 2. Description of combination systems. 3. Normal forms of Boolean algebra and their extract from maps. 4 - 5. Shannon expansion theorem and universal logic modules. Multiplexers, demultiplexers, decoders, encoders, value comparators, adders, parity generation and control, logic shifts. 6. Basic parallel and sequential commands of VHDL language. 7 - 8. Description of the operation of synchronous state machines in the intentions of the VHDL language at the register transfer levels. 9. - 13. Synchronous sequential function blocks (registers, counters and their applications), analysis and synthesis of synchronous state machines).

Exercises: The following is a program of lectures, focusing on the design of digital systems, their simulation and implementation in FPGA circuits.
Literature:
Peter Ševčík, Ján Kapitulík: Moderné prostriedky implementácie metód číslicového spracovania signálov II, Žilinská univerzita 2013, ISBN 978-80-554-0676-3
Gubiš, P.: Logické siete, VŠDS, 1985.
Jamrich, V. : Časti číslicových zariadení. ES VŠDS Žilina, 1990.
Matoušek D.: Číslicová technika - základy konstruktérske praxe, BEN - technická literatúra, Praha, 2001, ISBN 80-7300-025-3.
Pinker J., Poupa M.: Číslicové systémy a jazyk VHDL, BEN - technická literatúra, Praha, 2006, ISBN 80-7300-198-5
Instruction language: slovak/english
Notes:
Course evaluation::
Total number of evaluated students: 0
ABCDEFX
0 %0 %0 %0 %0 %0 %
ABCDEFX
0 %0 %0 %0 %0 %0 %
Course teachers:
Last updated: 2021-11-09 13:27:00.000
The person responsible for the course: doc. Ing. Peter Ševčík, PhD.
Approved by: prof. Ing. Pavel Segeč, PhD.
SOURCE: https://vzdelavanie.uniza.sk/vzdelavanie/planinfo.php?kod=274637&lng=en